1. Field of the Invention
This invention relates to a method and apparatus for use determining a planarization endpoint, during a chemical-mechanical polishing process, of a semiconductor wafer.
2. Discussion of the Related Art
In VLSI wiring technology, connecting metal lines are formed over a substrate containing device circuitry. These metal lines serve to electrically interconnect the discrete devices. These metal connecting lines are further insulated from the next interconnection level by thin films of insulating material formed by, for example, chemical vapor deposition (CVD) of oxide. In order to interconnect metal lines of different interconnection levels, holes are formed in the insulating layers to provide electrical access therebetween.
In such wiring processes, it is desirable that the insulating layers have a smooth surface topography, because rough surfaces cause fabrication problems. More specifically, it is difficult to image and pattern layers applied to rough surfaces, and this difficulty increases as the number of layers increases.
Recently chemical-mechanical (chem-mech) polishing (CMP) has been developed for providing smooth insulator topographies. CMP includes the use of polishing machines and other chemical-mechanical planarization processes. In these processes, it is important to remove a sufficient amount of material to provide a smooth surface, without removing an excessive amount of underlying materials. Thus, a precise etch endpoint detection technique is needed.
Presently, there are various types of lapping machines for reducing the thickness of semiconductor wafers. In general, these lapping machines include top and bottom lapping plates, between which the wafers are positioned. The two lapping plates are then moved relative to each other, and a slurry, consisting of an abrasive solution with or without an etching reagent, is fed between the plates to grind and flush away ground wafer particles. While lapping is typically associated with bulk removal of material from a wafer surface, chemical-mechanical polishing refers to polishing of thin films rather than bare wafers. In chemical-mechanical polishing, the slurry is fed between the lapping or polishing plates to polish and flush away the material removed. A chemical-mechanical polishing machine can include a single rotating polishing plate and a smaller diameter rotating wafer carrier to which a wafer (or wafers) is (are) mounted. The wafer carrier is held above the polishing plate, either in a stationary fixed position or oscillating back and forth in a predetermined path, while both polishing plate and wafer carrier are rotated about their respective center axes. A slurry, consisting of an abrasive suspension with or without an etching reagent, is fed onto the polishing plate during polishing of the wafer.
FIG. 1 shows an example of the formation of an interlevel contact stud 10 (FIG. 1(d)) between a first level metalization 12 and a second level metalization (not shown) in a high performance VLSI circuit 16. An interlevel dielectric 18 is deposited so as to conformally coat a lower level pattern 12 and fill gaps 20 between metallic lines 12. A rough surface 22 results which needs to be planarized prior to the next photoresist image being formed. Planarization is achieved upon polishing back a desired amount using CMP as indicated by the dotted line 24 in FIG. 1(b). The planarization is a consequence of using a polishing pad of an appropriate stiffness which transmits a higher pressure to the more elevated areas, thereby removing them more efficiently. Thin SiO.sub.2 and SiN.sub.x "cap" layers, 23a and 23b, respectively, are then deposited. Following via formation by reactive ion etching, a metalization layer 26 is blanket deposited (FIG. 1(c)). The metalization layer 26 is selectively polished back to produce planar metal studs 10 as shown in FIG. 1(d). A persistent difficulty in this process is the inability to determine when the required thickness 24 or endpoint has been reached during the first dielectric polishing step. One method of determining the required thickness or CMP endpoint is by using estimated CMP rates and time. CMP rates vary considerably with time, however, due to changes in polishing pad characteristics. Frequent stops are required in the fabrication process for ex-situ thickness measurements. This method is extremely time consuming and highly undesirable since operators must inspect each wafer after polish. Process throughput is thereby reduced and product yields are lowered. A more precise CMP endpoint detection method and apparatus is desired. In addition., while an endpoint for the second polishing step (metalization layer polish) can be achieved by inspection and observation of the blanket to patterned layer transition, automated endpoint detection would also be highly desirable.
An in-situ CMP endpoint determination method and apparatus is shown in U.S. Pat. No. 5,081,421, issued Jan. 14, 1992 and assigned to AT&T Bell Laboratories. In the '421 patent, the in-situ endpoint determination is based on a measurement of a voltage required to maintain a fixed current flow through a structure under polish. The voltage decreases linearly with the thickness of the dielectric. A disadvantage of the '421 patent endpoint CMP detector is its inability to provide endpoint measurement for polishing table speeds in excess of 20 to 25 rpm's for 5" wafers, such as 60 rpm, which are typical in many polishing applications wherein the maximum rpm is a function of wafer size. Another disadvantage of the '421 device is that it requires relatively high voltage operation (approximately 3 to 5 volts) which is incompatible for use in VLSI fabrication of low voltage (i.e., less than one-half volt) silicon junction devices.
In addition to the above-noted characteristics of CMP, removal uniformity can change during polishing of a wafer as a result of changes in pad and wafer carrier conditions. Detection of abnormal removal uniformity or spurious changes therein is therefore highly desirable, i.e., a method and apparatus for in-situ detection and monitoring of removal uniformity.
Thus, there remains a continuing need in the semiconductor fabrication art for an apparatus and method which accurately and efficiently detects and monitors polishing characteristics of a chemical-mechanical planarization process. A fast response time, low voltage device is highly desired.